 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| 1 p/n:pm0960 rev. 1.1, oct. 18, 2004 mx26f128j3 128m [x8/x16] single 3v page mode eliteflash tm memory features ? 3.0v to 3.6v operation voltage block structure - 128 x 128kbyte erase blocks fast random / page mode access time - 120/25 ns read access time - 150/25 ns read access time page depth: 4-word 128-bit protection register - 64-bit unique device identifier - 64-bit user programmable otp cells 32-byte write buffer - 6 us/byte effective programming time enhanced data protection features absolute protec- tion with vpen = gnd - flexible block locking - block erase/program lockout during power transi- tions performance low power dissipation - typical 15ma active current for page mode read - 80ua/(max.) standby current high performance - block erase time: 2s typ. - byte programming time: 210us typ. - block programming time: 0.8s typ. (using write to buffer command) program/erase endurance cycles: 100 cycles software feature support common flash interface (cfi) - eliteflash tm memory device parameters stored on the device and provide the host system to access. hardware feature a0 pin - select low byte address when device is in byte mode. not used in word mode. sts pin - indicates the status of the internal state machine. vpen pin - for erase /program/ block lock enable. vccq pin - the output buffer power supply, control the device 's output voltage. packaging - 56-lead tsop - 64-ball csp technology - 0.25u macronix nbit tm flash technology macronix nbit tm memory family
2 p/n:pm0960 rev. 1.1,oct. 18, 2004 mx26f128j3 general description the mxic's mx26f128j3 series eliteflash tm memory use the most advance 2 bits/cell nbit technology, double the storage capacity of memory cell. the device provide the high density eliteflash tm memory solution with reli- able performance and most cost-effective. the device organized as by 8 bits or by 16 bits of output bus. the device is packaged in 56-lead tsop and 64- ball csp. it is designed to be reprogrammed and erased in system or in standard eprom programmers. the device offers fast access time and allowing opera- tion of high-speed microprocessors without wait states. to eliminate bus contention, the device has separate chip enable (ce0, ce1, ce2) and output enable (oe) con- trols. the device augment eprom functionality with in- circuit electrical erasure and programming. the device uses a command register to manage this functionality. the mxic's nbit technology reliably stores memory con- tents even after the specific erase and program cycles. the mxic cell is designed to optimize the erase and program mechanisms by utilizing the dielectric's charac- ter to trap or release charges from ono layer. the device uses a 3.0v to 3.6v vcc supply to perform the high reliability erase and auto program/erase algo- rithms. the highest degree of latch-up protection is achieved with mxic's proprietary non-epi process. latch-up pro- tection is proved for stresses up to 100 milliamps on address and data pin from -1v to vcc + 1v. pin configuration 56 tsop (14mm x 20mm) a22 ce1 a21 a20 a19 a18 a17 a16 vcc a15 a14 a13 a12 ce0 vpen reset a11 a10 a9 a8 gnd a7 a6 a5 a4 a3 a2 a1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 nc we oe sts q15 q7 q14 q6 gnd q13 q5 q12 q4 vccq gnd q11 q3 q10 q2 vcc q9 q1 q8 q0 a0 byte a23 ce2 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 3 p/n:pm0960 rev. 1.1,oct. 18, 2004 mx26f128j3 symbol pin name a0 byte select address a1~a23 address input q0~q15 data inputs/outputs ce0, ce1, ce2 chip enable input we write enable input oe output enable input reset reset/power down mode pin description 64 ball csp (10x13x1.2mm, 1.0mm-ball pitch) notes: 1. don't use (du) pins refer to pins that should not be connected. a1 a b c d e f g h 1 2345 6 78 a2 a3 a4 q8 byte a6 gnd a7 a5 q1 q0 a8 a9 a10 a11 q9 q10 vpen ce0 a12 reset q3 q11 10mm a13 a14 a15 du q4 q12 vcc a18 du du du du du a19 a20 a16 q15 du a22 ce1 a21 13 mm a17 sts oe a23 ce2 a0 du q2 vcc vccq gnd q5 q13 q6 gnd q14 q7 we nc symbol pin name sts status pin byte byte mode enable vpen erase/program/block lock enable vccq output buffer power supply vcc device power supply gnd device ground nc pin not connected internally du don't use 4 p/n:pm0960 rev. 1.1,oct. 18, 2004 mx26f128j3 block diagram control input logic program/erase high voltage write s tat e machine (wsm) s tat e register array x-decoder address latch and buffer y-pass gate y-decoder array source hv command data decoder command data latch i/o buffer pgm data hv program data latch sense amplifier q0-q15 a0-a23 ce0 ce1 ce2 oe we reset 5 p/n:pm0960 rev. 1.1,oct. 18, 2004 mx26f128j3 figure 1. block architecture eliteflash tm memory reads erases and writes in-system via the local cpu. all bus cycles to or from the eliteflash tm memory conform to standard microprocessor bus cycles. table 1. chip enable truth table ce2 ce1 ce0 device vil vil vil enabled vil vil vih disabled vil vih vil disabled vil vih vih disabled vih vil vil enabled vih vil vih enabled vih vih vil enabled vih vih vih disabled note: for single-chip applications, ce2 and ce1 can be strapped to gnd. 01ffff 010000 00ffff 000000 64-kword block . . . 1 1fffff 1f0000 64-kword block 31 . . . 3fffff 3f0000 64-kword block 63 64-kword block word mode (x16) 03ffff 020000 01ffff 000000 . . . 3fffff 3e0000 . . . 7fffff a[23-0]: 128mbit a[23-1]: 128mbit 7e0000 ffffff fe0000 128-kbyte block 128-kbyte block 128-kbyte block 128-kbyte block byte mode (x8) 0 1 31 63 . . . 7fffff 7f0000 64-kword block . . . 128-kbyte block 127 127 0 128 mbit 6 p/n:pm0960 rev. 1.1,oct. 18, 2004 mx26f128j3 notes: 1. see table 1 on page 7 for valid ce configurations. 2. oe and we should never be enabled simultaneously. 3. dq refers to q0-q7 if byte is low and q0-q15 if byte is high. 4. refer to dc characteristics. when vpen < vpenlk , memory contents can be read, but not altered. 5. x can be vil or vih for control and address pins, and vpenlk or vpenh for vpen . see dc characteristics for vpenlk and vpenh voltages. 6. in default mode, sts is vol when the wsm is executing internal block erase, program, or lock-bit configuration algorithms. it is voh when the wsm is not busy, or in reset/power-down mode. 7. high z will be voh with an external pull-up resistor. 8. see section , "read identifier codes" for read identifier code data. 9. see section , "read query mode command" for read query data. 10.command writes involving block erase, program, or lock-bit configuration are reliably executed when vpen= vpenh and vcc is within specification. 11.refer to table 3 on page 10 for valid din during a write operation. table 2. bus operations command read output standby reset read id read read read write sequence array disable mode/ query status status power (wsm off) (wsm on) down mode notes 4,5,6 6,10,11 reset vih vih vih vil vih vih vih vih vih ce0,ce1,ce2(1) enabled enabled disabled x enabled enabled enabled enabled enabled oe (2) vil vih x x vil vil vil vil vih we (2) vih vih x x vih vih vih vih vil address x x x x see see x x x figure 2 table 6 vpen x x x x x x x x vpenh q (3) data out high z high z high z note 8 note 9 data out q7=data out data in q15-8=high z q6-0=high z sts high z x x high z high z high z x (default mode) (7) (7) (7) (7) 7 p/n:pm0960 rev. 1.1,oct. 18, 2004 mx26f128j3 function the device includes on-chip program/erase control cir- cuitry. the write state machine (wsm) controls block erase and byte/word/page program operations. opera- tional modes are selected by the commands written to the command user interface (cui). the status register indicates the status of the wsm and when the wsm successfully completes the desired program or block erase operation. read the device has three read modes, which accesses to the memory array, the device identifier or the status register independent of the vpen voltage. the appro- priate read command are required to be written to the cui. upon initial device powerup or after exit from powerdown, the device automatically resets to read ar- ray mode. in the read array mode, low level input to ce0, ce1, ce2 and oe, high level input to we and reset and address signals to the address inputs (a23-a0) out- put the data of the addressed location to the data input/ output (q15~q0). when reading information in read array mode, the de- vice defaults to asynchronous page mode. in this state, data is internally read and stored in a high-speed page buffer. a2:0 addresses data in the page buffer. the page size is 4 words or 8 bytes. asynchronous word/byte mode is supported with no additional commands required. write writes to the cui enables reading of memory array data, device identifiers and reading and clearing of the status register and when vpen=vpenh block erasure pro- gram and lock-bit configuration. the cui is written when the device is enable, we is active and oe is at high level. address and data are latched on the earlier rising edge of we and ce. standard micro-processor write tim- ings are used. output disable when oe is at vih, output from the devices is disabled. data input/output are in a high-impedance(high-z) state. standby when ce0, ce1 and ce2 disable the device (see table1) and place it in standby mode. the power consumption of this device is reduced. data input/output are in a high- impedance(high-z) state. if the memory is deselected during block erase, program or lock-bit configuration, the internal control circuits remain active and the device con- sume normal active power until the operation completes. power-down when reset pin is at vil the device is in the power- down mode and its power consumption is substantially low around 25ua. during read modes, the memory is deselected and the data input/output are in a high- impedance(high-z) state. to return from power down mode requires reset pin at vih. after return from powerdown, the cui is reset to read array , and the status register is set to value 80h. during block erase program or lock-bit configuration modes, reset pin at vil will abort either operation. memory array data of the block being altered become invalid. in default mode, sts transitions low and remains low for a maximum time of tplph+tphrh until the reset operation is complete. memory contents being altered are no longer valid; the data may be partially corrupted after a program or partially altered after an erase or lock- bit configuration. time tphwl is required after reset goes to logic-high (vih) before another command can be written. read query the read query operation outputs block status informa- tion, cfi (common flash interface) id string, system interface information, device geometry information and mxic extended query information. 8 p/n:pm0960 rev. 1.1,oct. 18, 2004 mx26f128j3 command definitions device operations are selected by writing specific address and data sequences into the cui. table 3 defines the valid register command sequences. when vpen 9 p/n:pm0960 rev. 1.1,oct. 18, 2004 mx26f128j3 notes: 1. bus operations are defined in table 2. 2. x = any valid address within the device. ba = address within the block. ia = identifier code address: see figure 2 and table 14. qa = query database address. pa = address of memory location to be programmed. rcd = data to be written to the read configuration register. this data is presented to the device on a 16-1 ; all other address inputs are ignored. 3. id = data read from identifier codes. qd = data read from query database. srd = data read from status register. see table 15 for a description of the status register bits. pd = data to be programmed at location pa. data is latched on the rising edge of we. cc = configuration code. 4. the upper byte of the data bus (q8-q15) during command writes is a "don't care" in x16 operation. 5. following the read identifier codes command, read operations access manufacturer, device and block lock codes. see section 4.3 for read identifier code data. 6. if the wsm is running, only q7 is valid; q15-q8 and q6-q0 float, which places them in a high impedance state. 7. after the write to buffer command is issued check the xsr to make sure a buffer is available for writing. 8. the number of bytes/words to be written to the write buffer = n + 1, where n = byte/word count argument. count ranges on this device for byte mode are n = 00h to n = 1fh and for word mode are n = 0000h to n =000fh. the third and consecutive bus cycles, as determined by n, are for writing data into the write buffer. the confirm command (d0h) is expected after exactly n + 1 write cycles; any other command at that point in the sequence aborts the write to buffer operation. please see figure 4. "write to buffer flowchart" for additional information. 9. the write to buffer or erase operation does not begin until a confirm command (d0h) is issued. 10.attempts to issue a block erase or program to a locked block. 11.either 40h or 10h are recognized by the wsm as the byte/word program setup. 12.the clear block lock-bits operation simultaneously clears all block lock-bits. 10 p/n:pm0960 rev. 1.1,oct. 18, 2004 mx26f128j3 figure 2. device identifier code memory map note: a0 is not used in either x8 or x16 mode when obtaining these identifier codes. data is always given on the low byte in x16 mode (upper byte contains 00h). 3fffff 3f0003 3f0002 3f0000 3effff block 63 reserved for future implementation reserved for future implementation (block 32 through 62) block 63 lock configuration 7fffff word address a[23-1]: 128 mbit 7f0003 7f0002 7f0000 7effff block 127 reserved for future implementation reserved for future implementation (block 64 through 126) block 127 lock configuration 1f0003 1f0002 1f0000 1effff 01ffff block 31 reserved for future implementation reserved for future implementation (block 2 through 30) block 31 lock configuration 010003 010002 010000 000003 000002 000001 000000 block 1 reserved for future implementation 00ffff 000004 block 0 reserved for future implementation reserved for future implementation block 1 lock configuration block 0 lock configuration device code manufacturer code 128 mbit 11 p/n:pm0960 rev. 1.1,oct. 18, 2004 mx26f128j3 read array command the device is in read array mode on initial device power up and after exit from power down, or by writing ffh to the command user interface. the read configuration reg- ister defaults to asynchronous read page mode. the de- vice remains enabled for reads until another command is written. the read array command functions indepen- dently of the vpen voltage. read query mode command this section defines the data structure or "database" returned by the common flash interface (cfi) query command. system software should parse this structure to gain critical information such as block size, density, x8/x16, and electrical specifications. once this informa- tion has been obtained, the software will know which command sets to use to enable eliteflash tm memory writes, block erases, and otherwise control the eliteflash tm memory component. query structure output the query database allows system software to gain in- formation for controlling the eliteflash tm memory com- ponent. this section describes the device cfi-compliant interface that allows the host system to access query data. query data are always presented on the lowest-order data outputs (dq 0-7) only. the numerical offset value is the address relative to the maximum bus width supported by the device. on this family of devices, the query table device starting address is a 10h, which is a word ad- dress for x16 devices. for a word-wide (x16) device, the first two bytes of the query structure, "q" and "r" in ascii, appear on the low byte at word addresses 10h and 11h. this cfi-com- pliant device outputs 00h data on upper bytes. thus, the device outputs ascii "q" in the low byte (dq 0-7 ) and 00h in the high byte (dq 8-15 ). at query addresses containing two or more bytes of in- formation, the least significant data byte is presented at the lower address, and the most significant data byte is presented at the higher address. 12 p/n:pm0960 rev. 1.1,oct. 18, 2004 mx26f128j3 word addressing byte addressing offset hex code v alue offset hex code value a15-a0 d15 - d0 a7-a0 d7 - d0 0010h 0051 "q" 20h 51 "q" 0011h 0052 "r" 21h 51 "q" 0012h 0059 "y" 22h 52 "r" 0013h p_id lo prvendor 23h 52 "r" 0014h p_id hi id# 24h 59 "y" 0015h plo prv endor 25h 59 "y" 0016h phi tbladr 26h p_id lo prvendor 0017h a_id lo altvendor 27h p_id lo id# 0018h a_id hi id# 28h p_id hi id# ... ... ... ... ... ... in all of the following tables, addresses and data are represented in hexadecimal notation, so the "h" suffix has been dropped. in addition, since the upper byte of word-wide devices is always "00h", the leading "00" has been dropped from the table notation and only the lower byte value is shown. any x16 device outputs can be assumed to have 00h on the upper byte in this mode. note: 1. the system must drive the lowest order addresses to access all the device's array data when the device is configured in x8 mode. therefore, word addressing, where these lower addresses are not toggled by the system, is "not applicable" for x8-configured devices. device query start location in query data with maximum query data with byte type/mode maximum device bus device bus width addressing addressing width addresses hex hex ascii hex hex ascii offset code v alue offset code v alue x16 device 10: 0051 "q" 20: 51 "q" x16 mode 10h 11: 0052 "r" 21: 00 "null" 12: 0059 "y" 22: 52 "r" x16 device 20: 51 "q" x8 mode n/a (1) n/a (1) 21: 51 "q" 22: 52 "r" table 4. summary of query structure output as a function of device and mode table 5. example of query structure output of a x16- and x8-capable device 13 p/n:pm0960 rev. 1.1,oct. 18, 2004 mx26f128j3 offset sub-section name description 00h manufacturer code 01h device code (ba+2)h (2) block status register block-specific information 04-0fh reserved reserved for vendor-specific information 10h cfi query identification string reserved for vendor-specific information 1bh system interface information command set id and vendor data offset 27h device geometry definition eliteflash tm memory device layout p (3) primary mxic-specific extended vendor-defined additional information specific to the query table pr imary vendor algorithm notes: 1. refer to the query structure output section and offset 28h for the detailed definition of offset address as a function of device bus width and mode. 2. ba = block address beginning location (i.e., 02000h is block 2s beginning location when the block size is 128 kbyte). 3. offset 15 defines "p" which points to the primary mxic-specific extended query table. table 6. query structure (1) block status register the block status register indicates whether an erase operation completed successfully or whether a given block is locked or can be accessed for eliteflash tm memory program/erase operations. offset length description address v alue (ba+2)h (1) 1 block lock status register ba+2: --00 or --01 bsr.0 block lock status 0 = unlocked ba+2: (bit 0): 0 or 1 1 = locked bsr 1-7: reserved for future use ba+2: (bit 1-7): 0 note: 1. ba = the beginning location of a block address (i.e., 008000h is block 1s (64-kb block) beginning location in word mode). table 7. block status register query structure overview the query command causes the eliteflash tm memory component to display the common flash interface (cfi) query structure or "database". the structure sub-sections and address locations are summarized below. 14 p/n:pm0960 rev. 1.1,oct. 18, 2004 mx26f128j3 offset length description add. hex v alue code 10h 3 query-unique ascii string "qry" 10 --51 "q" 11: --52 "r" 12: --59 "y" 13h 2 primary vendor command set and control interface id code. 13: --01 16-bit id code for vendor-specified algorithms 14: --00 15h 2 extended query table primary algorithm address 15: --31 16: --00 17h 2 alternate vendor command set and control interface id code. 17: --00 0000h means no second vendor-specified algorithm exists 18: --00 19h 2 secondary algorithm extended query table address. 19: --00 0000h means none exists 1a: --00 table 8. cfi identification offset length description add. hex v alue code 1bh 1 vcc logic supply minimum program/erase voltage bits 0-3 bcd 100 mv 1b: --30 3.0v bits 4-7 bcd volts 1ch 1 vcc logic supply maximum program/erase voltage bits 0-3 bcd 100 mv 1c: --36 3.6 v bits 4-7 bcd volts 1dh 1 vpp [programming] supply minimum program/erase voltage bits 0-3 bcd 100 mv 1d: --00 0.0v bits 4-7 hex volts 1eh 1 vpp [programming] supply maximum program/erase voltage bits 0-3 bcd 100 mv 1e: --00 0.0v bits 4-7 hex volts 1fh 1 "n" such that typical single word program time-out = 2 n us 1f: --07 128us 20h 1 "n" such that typical max. buffer write time-out = 2 n us 20: --07 128us 21h 1 "n" such that typical block erase time-out = 2 n ms 21: --0a 1s 22h 1 "n" such that typical full chip erase time-out = 2 n ms 22: --00 na 23h 1 "n" such that maximum word program time-out = 2 n times typical 23: --04 2ms 24h 1 "n" such that maximum buffer write time-out = 2 n times typical 24: --04 2ms 25h 1 "n" such that maximum block erase time-out = 2 n times typical 25: --04 16s 26h 1 "n" such that maximum chip erase time-out = 2 n times typical 26: --00 na system interface information the following device information can optimize system interface software. table 9. system interface information cfi query identification string the cfi query identification string provides verification that the component supports the common flash interface specification. it also indicates the specification version and supported vendor-specified command set(s). 15 p/n:pm0960 rev. 1.1,oct. 18, 2004 mx26f128j3 address 128m 27: --18 28: --02 29: --00 2a: --05 2b: --00 2c: --01 2d: --7f 2e: --00 2f: --00 30: --02 device geometry definition this field provides critical details of the eliteflash tm memory device geometry. offset length description code see table below 27h 1 "n" such that device size = 2 n in number of bytes 27: 28h 2 eliteflash tm memory device interface: x8 async(28:00,29:00), 28: --02 x8/x16 x16 async(28:01,29:00), x8/x16 async(28:02,29:00) 29: --00 2ah 2 "n" such that maximum number of bytes in write buffer = 2 n 2a: --05 32 2b: --00 number of erase block regions within device: 1. x = 0 means no erase blocking; the device erases in "bulk" 2. x specifies the number of device or partition regions with one or 2ch 1 more contiguous same-size erase blocks 2c: --01 1 3. symmetrically blocked partitions have one blocking region 4. partition size = (total blocks) x (individual block size) 2dh 4 erase block region 1 information 2d: bits 0-15 = y, y+1 = number of identical-size erase blocks 2e: bits 16-31 = z, region erase block(s) size are z x 256 bytes 2f: 30: table 10. device geometry definition device geometry definition 16 p/n:pm0960 rev. 1.1,oct. 18, 2004 mx26f128j3 offset(1) length description add. hex value p=31h (optional eliteflash tm memory features and commands) code (p+0)h 3 primary extended query table 31: --50 "p" (p+1)h unique ascii string "pri" 32: --52 "r" (p+2)h 33: --49 "i" (p+3)h 1 major version number, ascii 34: --31 "1" (p+4)h 1 minor version number, ascii 35: --32 "2" (p+5)h optional feature and command support (1=yes, 0=no) 36: --c8 (p+6)h bits 9-31 are reserved; undefined bits are "0". if bit 31 is 37: --00 (p+7)h "1" then another 31 bit field of optional features follows at 38: --00 (p+8)h the end of the bit-30 field. 39: --00 bit 0 chip erase supported bit 0 = 0 no 4 bit 1 reserved bit 1 = 0 bit 2 reserved bit 2 = 0 bit 3 legacy lock/unlock supported bit 3 = 1(1) y es(1) bit 4 queued erase supported bit 4 = 0 no bit 5 instant individual block locking supported bit 5 = 0 no bit 6 protection bits supported bit 6 = 1 yes bit 7 page-mode read supported bit 7 = 1 yes bit 8 synchronous read supported bit 8 = 0 no (p+9)h 1 reserved 3a: --00 (p+a)h block status register mask 3b: --01 (p+b)h 2 bits 2-15 are reserved; undefined bits are "0" 3c: --00 bit 0 block lock-bit status register active bit 0 = 1 yes bit 1 block lock-down bit status active bit 1 = 0 no (p+c)h 1 vcc logic supply highest performance program/erase voltage bits 0-3 bcd value in 100 mv 3d: --33 3.3v bits 4-7 bcd value in volts (p+d)h 1 vpp optimum program/erase supply voltage bits 0-3 bcd value in 100 mv 3e: --00 0.0v bits 4-7 hex value in volts primary-vendor specific extended query table certain eliteflash tm memory features and commands are optional. the primary vendor-specific extended query table specifies this and other similar information. note: 1. future devices may not support the described "legacy lock/unlock" function. thus bit 3 would have a value of "0". table 11. primary vendor-specific extended query 17 p/n:pm0960 rev. 1.1,oct. 18, 2004 mx26f128j3 offset(1) length description add. hex value p=31h (optional eliteflash tm memory features and commands) code (p+e)h 1 number of protection register fields in jedec id space. 3f: --01 01 "00h," indicates that 256 protection bytes are available protection field 1: protection description this field describes user-available one time programmable (otp) protection register bytes. some are pre-programmed (p+f)h with device-unique serial numbers. others are user-programmable. (p+10)h bits 0-15 point to the protection register lock 40: --00 00h (p+11)h byte, the section's first byte. the following bytes are factory (p+12)h pre-programmed and user-programmable. bits 0-7 = lock/bytes jedec-plane physical low address bits 8-15 = lock/bytes jedec-plane physical high address bits 16-23 = "n" such that 2 n = factory pre-programmed bytes bits 24-31 = "n" such that 2 n = user-programmable bytes note: 1. the variable p is a pointer which is defined at cfi offset 15h. table 12. protection register information offset(1) length description add. hex value p=31h (optional eliteflash tm memory features and commands) code page mode read capability bits 0-7 = "n" such that 2 n hex value represents the number (p+13)h 1 of read- page bytes. see offset 28h for device word width to 44: --03 8 byte determine page-mode data output width. 00h indicates no read page buffer. (p+14)h 1 number of synchronous mode read configuration fields that 45: --00 0 follow. 00h indicates no burst capability. (p+15)h reserved for future use 46: note: 1. the variable p is a pointer which is defined at cfi offset 15h. table 13. page read information 18 p/n:pm0960 rev. 1.1,oct. 18, 2004 mx26f128j3 notes: 1. the lowest order address line is a0. 2. x selects the specific blocks lock configuration code. device operation silicon id read the silicon id read mode allows the reading out of a binary code from the device and will identify its manu- facturer and type. this mode is intended for use by programming equipment for the purpose of automatically matching the device to be programmed with its corre- sponding programming algorithm. this mode is func- tional over the entire temperature range of the device. to activate this mode, the two cycle "silicon id read" command is requested. (the command sequence is il- lustrated in table 14. during the "silicon id read" mode, manufacturer's code (mxic=c2h) can be read out by setting a0=vil and device identifier can be read out by setting a0=vih. to terminate the operation, it is necessary to write the read command. the "silicon id read" command func- tions independently of the vpen voltage. this command is valid only when the wsm is off. table 14. mx26f128j3 silicon id codes and verify sector protect code type address (1) code (hex) q7 q6 q5 q4 q3 q2 q1 q0 manufacture code 00000 c2h 1 1 0 0 0 0 1 0 device code 00001 (00) 74h 0 1 1 1 0 1 0 0 block lock configuration x0002 (2) - block is unlocked dq0=0 - block is locked dq0=1 - reserved for future use dq1-7 19 p/n:pm0960 rev. 1.1,oct. 18, 2004 mx26f128j3 high z definition symbol when status notes busy? "1" "0" sr.7 no write state machine status ready busy 1 sr.6 yes reserved sr.5 yes erase and clear lock-bits error in block erasure or successful block 2 status clear lock-bits erase or clear lock-bits sr.4 yes program and set lock-bit error in setting lock-bit successful set block status lock bit sr.3 yes programming voltage low progr amming voltage programming voltage 3 status detected, operation ok aborted sr.2 yes reserved sr.1 yes device protect status block lock-bit detected, unlock 4 operation abort sr.0 yes reserved 5 table 15. status register definitions notes 1. check sts or sr.7 to determine block erase, program, or lock-bit configuration completion. sr.6-sr.0 are not driven while sr.7 = 0 2. if both sr.5 and sr.4 are "1" after a block erase or lock-bit configuration attempt, an improper command se- quence was entered. 3. sr.3 does not provide a continuous programming voltage level indication. the wsm interrogates and indicates the programming voltage level only after block erase, program, set block lock-bit, or clear block lock-bits com- mand sequences. 4. sr.1 does not provide a continuous indication of block lock-bit values. the wsm interrogates the block lock-bits only after block erase, program, or lock-bit configuration command sequences. it informs the system, depend- ing on the attempted operation, if the block lock-bit is set. read the block lock configuration codes using the read identifier codes command to determine block lock-bit status. 5. sr.0 is reserved for future use and should be masked when polling the status register. high z definition symbol when status notes busy? "1" "0" xsr.7 no write buffer status write buffer available write buffer not available 1 xsr.6- yes reserved 2 xsr.0 table 16 . extended status register definitions notes: 1. after a buffer-write command, xsr.7 = 1 indicates that a write buffer is available. 2. xsr.6-xsr.0 are reserved for future use and should be masked when polling the status register. 20 p/n:pm0960 rev. 1.1,oct. 18, 2004 mx26f128j3 block erase command automated block erase is initiated by writing the block erase command of 20h followed by the confirm com- mand of d0h. an address within the block to be erased is required (erase changes all block data to ffh). block preconditioning, erase, and verify are handled in- ternally by the wsm (invisible to the system). the cpu can detect block erase completion by analyzing the out- put of the sts pin or status register bit sr.7. toggle oe, ce0 , ce1 , or ce2 to update the status register. the cui remains in read status register mode until a new command is issued. also, reliable block erasure can only occur when vcc is valid and vpen = vpenh. write to buffer command to program the device, a write to buffer command is issue first. a variable number of bytes, up to the buffer size, can be loaded into the buffer and written to the eliteflash tm memory device. first, the write to buffer setup command is issued along with the block address (see figure 4 ,"write to buffer flowchart" on page26). after the command is issued, the extended status reg- ister (xsr) can be read when ce is vil. xsr.7 indi- cates if the write buffer is available. if the buffer is available, the number of words/bytes to be program is written to the device. next, the start ad- dress is given along with the write buffer data. subse- quent writes provide additional device addresses and data, depending on the count. after the last buffer data is given, a write confirm command must be issued. the wsm beginning copy the buffer data to the eliteflash tm memory array. if an error occurs while writing, the device will stop writ- ing, and status register bit sr.4 will be set to a "1" to indicate a program failure. the internal wsm verify only detects errors for "1" that do not successfully program to "0" . if a program error is detected, the status register should be cleared. any time sr.4 and/or sr.5 is set, the device will not accept any more write to buffer com- mands. reliable buffered writes can only occur when vcc is valid and vpen = vpenh. also, successful program- ming requires that the corresponding block lock-bit be reset. byte/word program commands byte/word program is executed by a two-command se- quence. the byte/word program setup command of 40h is written to the command interface, followed by a sec- ond write specifying the address and data to be written. the wsm controls the program pulse application and verify operation. the cpu can detect the completion of the program event by analyzing the sts pin or status register bit sr.7. if a byte/word program is attempted while vpen_v penlk, status register bits sr.4 and sr.3 will be set to "1". successful byte/word programs require that the cor- responding block lock-bit be cleared. if a byte/ word pro- gram is attempted when the corresponding block lock- bit is set, sr.1 and sr.4 will be set to "1". read status register command the status register is read after writing the read status register command of 70h to the command user inter- face. also, after starting the internal operation the de- vice is set to the read status register mode automati- cally. the contents of status register are latched on the later falling edge of oe or the first edge of ce0, ce1, ce2 that enables the device oe must be toggle to vih or the device must be disable before further reads to update the status register latch. the read status register com- mand functions independently of the vpen voltage. clear status register command the erase status, program status, block status bits and protect status are set to "1" by the write state ma- chine and can only be reset by the clear status register command of 50h. these bits indicates various failure conditions. 21 p/n:pm0960 rev. 1.1,oct. 18, 2004 mx26f128j3 read configuration the device will support both asynchronous page mode and standard word/byte reads. no configuration is required. status register and identifier only support standard word/byte single read operations. table 17. read configuration register definition rm r r r r r r r 16(a16) 15 14 13 12 11 10 9 rr r r r r r r 87 6 5 4 3 2 1 notes rcr.16 = read mode (rm) read mode configuration effects reads from the 0 = standard word/byte reads enabled (default) eliteflash tm memory array. 1 = page-mode reads enabled status register, query, and identifier reads support standard word/byte read cycles. rcr.15-1= reserved for future these bits are reserved for future use. set these enhancements (r) bits to "0". configuration command the status (sts) pin can be configured to different states using the configuration command. once the sts pin has been configured, it remains in that configuration until another configuration command is issued or rp is asserted low. initially, the sts pin defaults to ry/by operation where ry/by low indicates that the state machine is busy. ry/by high indicates that the state machine is ready for a new operation. table 19, "configuration coding definitions" on page 28 displays the possible sts configurations. to reconfigure the status (sts) pin to other modes, the configuration command is given followed by the desired configuration code. the three alternate configurations are all pulse mode for use as a system interrupt as described below. for these configurations, bit 0 controls erase complete interrupt pulse, and bit 1 controls program complete interrupt pulse. supplying the 00h configuration code with the configuration command resets the sts pin to the default ry/by level mode. the possible configurations and their usage are described in table 19, "configuration coding definitions" on page 28. the configuration command may only be given when the device is not busy. check sr.7 for device status. an invalid configuration code will result in both status register bits sr.4 and sr.5 being set to "1". when configured in one of the pulse modes, the sts pin pulses low with a typical pulse width of 250 ns. 22 p/n:pm0960 rev. 1.1,oct. 18, 2004 mx26f128j3 q7 - q2 = reserved q1 - q0 = sts pin configuration codes 00 = default, level mode ry/by (device ready) indication 01 = pulse on erase complete 10 = pulse on program complete 11 = pulse on erase or program complete configuration codes 01b, 10b, and 11b are all pulse mode such that the sts pin pulses low then high when the operation indicated by the given configuration is completed. configuration command sequences for sts pin configuration (masking bits q7- q 2 to 00h) are as follows: default ry/by level mode: b8h, 00h er int (erase interrupt): b8h, 01h pulse-on-erase complete pr int (program interrupt): b8h, 02h pulse-on-program complete er/pr int (erase or program interrupt): b8h, 03h pulse-on-erase or program complete table 18. configuration coding definitions note: 1. when the device is configured in one of the pulse modes, the sts pin pulses low with a typical pulse width of 250 ns. reserved pulse on pulse on program erase complete (1) compete (1) bits7-2 bit 1 bit 0 q7 - q2 are reserved for future use. default (q1-q 0 = 00) ry/by, level mode - used to control hold to a memory controller to prevent accessing a eliteflash tm memory subsystem while any eliteflash tm memory device's wsm is busy. configuration 01 er int, pulse mode - used to generate a system interrupt pulse when any eliteflash tm memory device in an array has completed a block erase. helpful for reformatting blocks after file system free space reclamation or "cleanup" configuration 10 pr int, pulse mode -used to generate a system interrupt pulse when any eliteflash tm memory device in an array has complete a program operation. provides highest performance for servicing continuous buffer write operations. configuration 11 er/pr int, pulse mode -used to generate system interrupts to trigger servic- ing of eliteflash tm memory arrays when either erase or program operations are completed when a common interrupt service routine is desired. 23 p/n:pm0960 rev. 1.1,oct. 18, 2004 mx26f128j3 set block lock-bit commands this device provided the block lock-bits, to lock and unlock the individual block. to set the block lock-bit, the two cycle set block lock-bit command is requested. this command is invalid while the wsm is running. writ- ing the set block lock-bit command of 60h followed by confirm command and an appropriate block address. after the command is written, the device automatically outputs status register data when read. the cpu can detect the completion of the set lock-bit event by ana- lyzing the sts pin output or status register bit sr.7. also, reliable operations occur only when vcc and vpen are valid. with vpen _vpenlk , lock-bit contents are protected against alteration. clear block lock-bits command all set block lock-bits can clear by the clear block lock- bits command. this command is invalid while the wsm is running. to clear the block lock-bits, two cycle com- mand is requested . the device automatically outputs status register data when read. the cpu can detect completion of the clear block lock-bits event by analyz- ing the sts pin output or status register bit sr.7. if a clear block lock-bits operation is aborted due to v pen or vcc transiting out of valid range, block lock-bit values are left in an undetermined state. a repeat of clear block lock-bits is required to initialize block lock-bit contents to known values. protection register program command the device offer a 128-bit protection register to increase the security of a system design. the 128-bits protection register are divided into two 64-bit segments. one is pro- grammed in the factory with a unique 64-bit number, which is unchangeable. the other one is left blank for customer designers to program as desired. once the customer segment is programmed, it can be locked to prevent reprogramming. reading the protection register the protection register is read in the identification read mode. the device is switched to this mode by writing the read identifier command 90h. once in this mode, read cycles from addresses retrieve the specified informa- tion. to return to read array mode, write the read array command (ffh). programming the protection register the protection register bits are programmed using the two-cycle protection program command. the 64-bit num- ber is programmed 16 bits at a time for word-wide parts and eight bits at a time for byte-wide parts. first write the protection program setup command, c0h. the next write to the device will latch in address and data and program the specified location. any attempt to address protection program commands outside the defined protection register address space will result in a status register error. attempting to program a locked protection register segment will result in a status register error. locking the protection register the user-programmable segment of the protection regis- ter is lockable by programming bit 1 of the pr-lock location to 0. bit 0 of this location is programmed to 0 at the mxic factory to protect the unique device number. bit 1 is set using the protection program command to program "fffd" to the pr-lock location. after these bits have been programmed, no further changes can be made to the values stored in the protection register. pro- tection program commands to a locked section will re- sult in a status register error. protection register lockout state is not reversible. vcc transitions block erase, program, and lock-bit configuration are not guaranteed if vcc falls outside of the specified operat- ing ranges. the cui latches commands issued by system software and is not altered by ce transitions, or wsm actions. its state is read array mode upon power-up, after exit from power-down mode, or after vcc transitions below vlko. 24 p/n:pm0960 rev. 1.1,oct. 18, 2004 mx26f128j3 figure 3. protection register memory map note: a 0 is not used in x16 mode when accessing the protection register map (see table 20 for x16 addressing). for x8 mode a 0 is used (see table 21 for x8 addressing). 88h word address 85h 4 words user programmed a[23 -1]: 128 mbit 84h 81h 80h 4 words factory programmed 1 word lock 25 p/n:pm0960 rev. 1.1,oct. 18, 2004 mx26f128j3 table 20. word-wide protection register addressing word use a8 a7 a6 a5 a4 a3 a2 a1 lock both 1 0 0 0 0 0 0 0 0 factory 1 0 0 0 0 0 0 1 1 factory 1 0 0 0 0 0 1 0 2 factory 1 0 0 0 0 0 1 1 3 factory 1 0 0 0 0 1 0 0 4 user 1 0 0 0 0 1 0 1 5 user 1 0 0 0 0 1 1 0 6 user 1 0 0 0 0 1 1 1 7 user 1 0 0 0 1 0 0 0 note: 1. all address lines not specified in the above table must be 0 when accessing the protection register, i.e., a23-a9 = 0. table 21. byte-wide protection register addressing word use a8 a7 a6 a5 a4 a3 a2 a1 a0 lock both 1 0 0 0 0 0 0 0 0 lock both 1 0 0 0 0 0 0 0 1 0 factory 1 0 0 0 0 0 0 1 0 1 factory 1 0 0 0 0 0 0 1 1 2 factory 1 0 0 0 0 0 1 0 0 3 factory 1 0 0 0 0 0 1 0 1 4 factory 1 0 0 0 0 0 1 1 0 5 factory 1 0 0 0 0 0 1 1 1 6 factory 1 0 0 0 0 1 0 0 0 7 factory 1 0 0 0 0 1 0 0 1 8 user 1 0 0 0 0 1 0 1 0 9 user 1 0 0 0 0 1 0 1 1 a user 1 0 0 0 0 1 1 0 0 b user 1 0 0 0 0 1 1 0 1 c user 1 0 0 0 0 1 1 1 0 d user 1 0 0 0 0 1 1 1 1 e user 1 0 0 0 1 0 0 0 0 f user 1 0 0 0 1 0 0 0 1 note: 1. all address lines not specified in the above table must be 0 when accessing the protection register, i.e., a23-a9 = 0. 26 p/n:pm0960 rev. 1.1,oct. 18, 2004 mx26f128j3 figure 4. write to buffer flowchart start end command cycle - issue write-to-buffer command - address=any address in block - data=0xe8 check ready status - read status register command not required - perform read operation - read ready status on signal d7 write word count - address=any address in block - data=word count - valid range=0x0 thru 0x1f write buffer data - fill write buffer up to word count - address=address(es) within buffer range - data=data to be written no no no yes yes yes confirm cycle - issue confirm command - address=any address in block - data=0xd0 read status register see status register flowchart d7=1? write to buffer time-out ? any errors? error-handler user-defined routine 27 p/n:pm0960 rev. 1.1,oct. 18, 2004 mx26f128j3 figure 5. status register flowchart start sr7 = '1' sr2 = '1' sr4 = '1' sr3 = '1' sr1 = '1' yes yes yes no no no no sr6 = '1' yes no sr5 = '1' no no error command sequence yes yes yes error erase failure error program failure -setbywsm - reset by user - see clear status register command - set/reset by wsm sr4 = '1' yes no end command cycle - issue status register command - address = any device address - data = 0x70 erase suspend see suspend/resume flowchart program suspend see suspend/resume flowchart error v pen 29 p/n:pm0960 rev. 1.1,oct. 18, 2004 mx26f128j3 figure 7. block erase flowchart start write 20h to block address erase eliteflash tm memory block(s) completed full status check if desired write confirm d0h to block address read status register no yes sr.7=1 ? 30 p/n:pm0960 rev. 1.1,oct. 18, 2004 mx26f128j3 figure 8. set block lock-bit flowchart start write 60h, block address set lock-bit completed full status check if desired write 01h, block address read status register no yes sr.7=1 ? read status register data (see above) full status check procedure set lock-bit successful sr.3=0 ? yes no yes voltage range error no command sequence error yes set lock-bit error no sr.4,5=1 ? sr.4=0 ? 31 p/n:pm0960 rev. 1.1,oct. 18, 2004 mx26f128j3 figure 9. clear lock-bit flowchart start write 60h set lock-bit completed full status check if desired write d0h read status register no yes sr.7=1 ? read status register data (see above) full status check procedure clear block lock-bit successful sr.3=0 ? yes no yes voltage range error no command sequence error yes clear block lock-bits error no sr.4,5=1 ? sr.5=0 ? 32 p/n:pm0960 rev. 1.1,oct. 18, 2004 mx26f128j3 figure 10. protection register programming flowchart start write c0h (protection reg. program setup) program completed full status check if desired write protect. register address/data read status register no yes sr.7=1 ? read status register data (see above) full status check procedure program successful sr.3, sr.4= yes vpen range error 1,1 1,1 protection register programming error 0,1 attempted program to locked register-aborted sr.1, sr.4= sr.1, sr.4= 33 p/n:pm0960 rev. 1.1,oct. 18, 2004 mx26f128j3 absolute maximum ratings storage temperature plastic packages . . . . . . . . . . . . . ..... -65 o c to +150 o c ambient temperature with power applied. . . . . . . . . . . . . .... -65 o c to +125 o c voltage with respect to ground vcc (note 1) . . . . . . . . . . . . . . . . . -0.5 v to +4.0 v oe, and reset (note 2) . . . . . . . .-0.5 v to +12.5 v all other pins (note 1) . . . . . . . -0.5 v to vcc +0.5 v output short circuit current (note 3) . . . . . . 200 ma notes: 1. minimum dc voltage on input or i/o pins is -0.5 v. during voltage transitions, input or i/o pins may over- shoot vss to -2.0 v for periods of up to 20 ns. see figure 6. maximum dc voltage on input or i/o pins is vcc +0.5 v. during voltage transitions, input or i/o pins may overshoot to vcc +2.0 v for periods up to 20 ns. see figure 7. 2. minimum dc input voltage on pins oe and reset is -0.5 v. during voltage transitions oe and reset may overshoot vss to -2.0 v for periods of up to 20 ns. see figure 6. 3. no more than one output may be shorted to ground at a time. duration of the short circuit should not be greater than one second. stresses above those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those in- dicated in the operational sections of this data sheet is not implied. exposure of the device to absolute maxi- mum rating conditions for extended periods may affect device reliability. operating ratings commercial (c) devices ambient temperature (t a ). . . . . . . . . . . . 0 c to +70 c v cc supply voltages v cc for full voltage range. . . . . . . . . . . . .+3.0 v to 3.6 v operating ranges define those limits between which the functionality of the device is guaranteed. 34 p/n:pm0960 rev. 1.1,oct. 18, 2004 mx26f128j3 symbol parameter notes typ max unit t est conditions ili input and v pen load current 1 1 ua vcc = vcc max; vccq = vccq max vin = vccq or gnd ilo output leakage current 1 10 ua vcc = vcc max; vccq = vccq max vin = vccq or gnd cmos inputs, vcc = vcc max, icc1 vcc standby current 1,2,3 25 80 ua device is disabled (see table 2) reset=vccq 0.2v 0.71 2 ma ttl inputs, vcc=vcc max, device is disable (see table 2), reset=vih icc2 vcc power-down current 25 80 ua reset=gnd 0.2v iout(sts)=0ma cmos inputs, vcc=vcc max, vccq=vccq max 15 20 ma device is enabled (see table 2) icc3 vcc page mode read current 1,3 f=5mhz, iout=0ma cmos inputs, vcc=vcc max, vccq=vccq max 24 29 ma device is enabled (see table 2) f=33mhz, iout=0ma icc5 vcc program or set lock-bit 1,4 35 60 ma cmos inputs, vpen=vcc current 40 70 ma ttl inputs, vpen=vcc icc6 vcc block erase or clear 1,4 35 70 ma cmos inputs, vpen=vcc block lock-bits current 40 80 ma ttl inputs, vpen=vcc dc characteristics 35 p/n:pm0960 rev. 1.1,oct. 18, 2004 mx26f128j3 symbol parameter notes min max unit t est conditions vil input low voltage 3 -0.5 0.8 v vih input high voltage 3 2.0 vccq+0.5 v 0.4 v vccq=vccq2/3 min iol=2ma vol output low voltage 1,3 0.2 v vccq=vccq2/3 min iol=100ua 0.85 x v vccq=vccq min vccq ioh=-2.5ma voh output high voltage 1,3 vccq-0.2 v vccq=vccq min ioh=-100ua vpenlk vpen lockout during program, 3,5,6 0.5 vcc v erase and lock-bit operations vpenh vpen during block erase, 5,6 3.0 3.6 v program, or lock-bit operations vlko vcc lockout voltage 7 2.2 v dc characteristics, continued notes: 1. includes sts. 2. cmos inputs are either vcc 0.2 v or gnd 0.2 v. ttl inputs are either vil or vih . 3. sampled, not 100% tested. 4. iccws and icces are specified with the device de-selected. 5. block erases, programming, and lock-bit configurations are inhibited when v pen ? v penlk , and not guaranteed in the range between vpenlk (max) and vpenh (min), and above vpenh (max). 6. typically, vpen is connected to vcc (3.0 v - 3.6 v). 7. block erases, programming, and lock-bit configurations are inhibited when vcc < vlko , and not guaranteed in the range between vlko (min) and vcc (min), and above vcc (max). 36 p/n:pm0960 rev. 1.1,oct. 18, 2004 mx26f128j3 figure 11. transient input/output reference waveform for vccq=3.0v-3.6v test points vccq/2 output note:ac test inputs are driven at vccq for a logic "1" and 0.0v for a logic "0". input timing being, and output timing ends, at vccq/2v (50% of vccq). input rise and fall times (10% tp 90%)<5ns. vccq 0.0 input vccq/2 figure 12. transient equivalent testing load circuit note: cl includes jig capacitance test configuration c l (pf) vccq = vcc = 3.0 v-3.6 v 30 device under test cl out rl=3.3k ohm 1.3v 1n914 37 p/n:pm0960 rev. 1.1,oct. 18, 2004 mx26f128j3 versions vcc 3.0v-3.6v(3) (all units in ns unless otherwise noted) vccq 3.0v-3.6v(3) 120 150 sym parameter notes min max min max tavav read/write cycle time 120 150 tavqv address to output delay 120 150 telqv cex to output delay 120 150 tglqv oe to no n-array output delay 2, 4 50 50 tphqv reset high to output delay 210 210 telqx cex to output in low z 5 0 0 tglqx oe to output in low z 5 0 0 tehqz cex high to output in high z 5 35 35 tghqz oe high to output in high z 5 15 15 toh output hold from address, cex, or oe 5 0 0 change, whichever occurs first telfl/telfh cex low to byte high or low 5 10 10 tflqv/tfhqv byte to output delay 1000 1000 tflqz byte to output in high z 5 1000 1000 tehel cex high to cex low 5 0 0 tapa page address access time 5, 6 25 25 tglqv oe to array output delay 4 25 25 ac characteristics --read-only operations (1,2) notes:cex low is defined as the first edge of ce0 , ce1 , or ce2 that enables the device. cex high is defined at the first edge of ce0, ce1, or ce2 that disables the device (see table 2). 1. see ac input/output reference waveforms for the maximum allowable input slew rate. 2. oe may be delayed up to t elqv -t glqv after the first edge of ce0, ce1, or ce2 that enables the device (see table 2) without impact on t elqv . 3. see figures 14-16, transient input/output reference waveform for vccq = 3.0v - 3.6v, transient equivalent testing load circuit for testing characteristics. vcc = 3.0v - 3.6v. 4. when reading the eliteflash tm memory array a faster tglqv (r16) applies. non-array reads refer to status register reads, query reads, or device identifier reads. 5. sampled, not 100% tested. 6. for devices configured to standard word/byte read mode, r15 (tapa) will equal r2 (tavqv). 38 p/n:pm0960 rev. 1.1,oct. 18, 2004 mx26f128j3 figure 13. ac waveform for both page-mode and standard word/byte read operations note: 1. ce x low is defined as the first edge of ce0 , ce1 , or ce2 that enables the device. ce x high is defined at the first edge of ce0, ce1, or ce2 that disables the device (see table 2). 2. for standard word/byte read operations, tapa will equal tavqv. 3. when reading the eliteflash tm memory array a faster tglqv applies. non-array reads refer to status register reads, query reads, or device identifier reads. tavqv tavav tapa tglqx telqx tehqz tehel tghqz toh telfl/telfh tflqv/tfhqv tflqz telqv tglqv high z tphqv valid address valid address valid output valid output valid address valid address valid output valid output high z address (a23-a3) vih vil vih vil vih disable enable vil vih vil address (a2-a0) cex[e] oe [g] vih vil we [w] vih vil vcc vih vil reset[p] vih vil byte [f] voh vol data[d/q] q0- q15 39 p/n:pm0960 rev. 1.1,oct. 18, 2004 mx26f128j3 ac characteristics--write operations (1,2) versions valid for all speeds unit symbol parameter notes min max tphwl (tphel ) reset high recovery to we(cex) going low 3 210 ns telwl (twlel ) cex (we) low to we(cex) going low 4 0 ns twp write pulse width 4 70 ns tdvwh (tdveh ) data setup to we(cex) going high 5 50 ns tavwh (taveh ) address setup to we(cex) going high 5 55 ns twheh (tehwh) cex (we) hold from we(cex) high 0 ns twhdx (tehdx) data hold from we(cex) high 0 ns twhax (tehax) address hold from we(cex) high 0 ns twph wr ite pulse width high 6 30 ns tvpwh (tvpeh) vpen setup to we(cex) going high 3 0 ns twhgl (tehgl) write recovery before read 7 35 ns twhrl (tehrl) we(cex) high to sts going low 8 500 ns tqvvl vpen hold from valid srd, sts going high 3,8,9 0 ns twhqv5 (tehqv5) set lock-bit time 4,9 64 75/85 us twhqv6 (tehqv6) clear block lock-bits time 4 0.5 2 sec notes: cex low is defined as the first edge of ce0, ce1, or ce2 that enables the device. cex high is defined at the first edge of ce0, ce1, or ce2 that disables the device (see table 2). 1. read timing characteristics during block erase, program, and lock-bit configuration operations are the same as during read-only operations. refer to ac characteristics-read-only operations. 2. a write operation can be initiated and terminated with either ce x or we. 3. sampled, not 100% tested. 4. write pulse width (twp) is defined from cex or we going low (whichever goes low last) to cex or we going high (whichever goes high first). hence, twp = twlwh = teleh = twleh = telwh. 5. refer to table 4 for valid a in and d in for block erase, program, or lock-bit configuration. 6. write pulse width high (t wph) is defined from cex or we going high (whichever goes high first) to cex or we going low (whichever goes low first). hence, twph = twhwl = tehel = twhel = tehwl . 7. for array access, tavqv is required in addition to twhgl for any accesses after a write. 8. sts timings are based on sts configured in its ry/by default mode. 9. vpen should be held at vpenh until determination of block erase, program, or lock-bit configuration success (sr.1/3/4/5=0). 40 p/n:pm0960 rev. 1.1,oct. 18, 2004 mx26f128j3 figure 14. ac waveform for write operations notes: 1. cex low is defined as the first edge of ce0 , ce1 , or ce2 that enables the device. cex high is defined at the first edge of ce0, ce1, or ce2 that disables the device (see table 2). sts is shown in its default mode (ry/by). a. vcc power-up and standby. b. write block erase, write buffer, or program setup. c. write block erase or write buffer confirm, or valid address and data. d. automated erase delay. e. read status register or query data. f. write read array command. tvpwh (tvpeh) twhrl (tehrl) tqvvl twhqz/twhrh twph tavwh (taveh) tphwl (tphel) twp twhdx (tehdx) twheh (tehwh) twhax (tehax) telwl (twlel) tovwh (tdveh) twhgl (tehgl) din address (a) ab cd e f vih vil oe vih vil vih disable enable vil cex,(we)[e(w)] vih disable enable vil we,(cex)[w(e)] vih vil data[d/q] voh vol sts[r] vih vil vpenh vpenlk vil reset [p] vpen[v] din ain ain din valid srd 41 p/n:pm0960 rev. 1.1,oct. 18, 2004 mx26f128j3 figure 15. ac waveform for reset operation note: 1. sts is shown in its default mode (ry/by). sym parameter notes min max unit tplph reset pulse low time 2 35 us (if reset is tied to vcc , this specification is not applicable) tphrh reset high to reset during block erase, program, or 3 100 ns lock-bit configuration notes: 1. these specifications are valid for all product versions (packages and speeds). 2. if reset is asserted while a block erase, program, or lock-bit configuration operation is not executing then the minimum required reset pulse low time is 100ns. 3. a reset time, tphqv, is required from the latter of sts (in ry/by mode) or reset going high until outputs are valid. reset specifications (1) tphrh tplph vih vil sts (r) vih vil reset (p) 42 p/n:pm0960 rev. 1.1,oct. 18, 2004 mx26f128j3 limits parameter min. typ.(2) max. units block erase time 2.0 15.0 sec write buffer byte program time 218 900 us (time to program 32 bytes/16 words) byte program time (using word/byte program command) 210 900 us block program time (using write to buffer command) 0.8 2.4 sec block erase/program cycles 100 cycles erase and programming performance(1) note: 1.not 100% tested, excludes external system level over head. 2.typical values measured at 25 c,3.3v. additionally programming typically assume checkerboard pattern. parameter test conditions min unit minimum pattern data retention time 150 10 years 125 20 years data retention min. max. input voltage with respect to gnd on oe -1.0v 12.5v input voltage with respect to gnd on all power pins, address pins, ce and we -1.0v 2 vccmax input voltage with respect to gnd on all i/o pins -1.0v vcc + 1.0v current -100ma +100ma includes all pins except vcc. test conditions: vcc = 3.0v, one pin at a time. latch-up characteristics parameter symbol parameter description test set typ max unit cin input capacitance vin=0 6 7.5 pf cout output capacitance vout=0 8.5 12 pf cin2 control pin capacitance vin=0 7.5 9 pf capacitance ta=0 c to 70 c, vcc=3.0v~3.6v notes: 1. sampled, not 100% tested. 2. test conditions ta=25 c, f=1.0mhz 43 p/n:pm0960 rev. 1.1,oct. 18, 2004 mx26f128j3 ordering information plastic package part no. access time package type (ns) mx26f128j3tc-12 120/25 56-tsop mx26f128j3xcc-12 120/25 64-csp mx26f128j3tc-15 150/25 56-tsop MX26F128J3XCC-15 150/25 64-csp 44 p/n:pm0960 rev. 1.1,oct. 18, 2004 mx26f128j3 package information 45 p/n:pm0960 rev. 1.1,oct. 18, 2004 mx26f128j3 46 p/n:pm0960 rev. 1.1,oct. 18, 2004 mx26f128j3 revision history revision no. description page date 1.0 1. removed part no. mx26f640j3 all jun/30/2004 2. to add "eliteflash tm " and "nbit tm " trademark all 1.1 1. to add 120ns speed grade p1,37,43 oct/18/2004 mx26f128j3 m acronix i nternational c o., l td . headquarters: tel:+886-3-578-6688 fax:+886-3-563-2888 europe office : tel:+32-2-456-8020 fax:+32-2-456-8021 hong kong office : tel:+86-755-834-335-79 fax:+86-755-834-380-78 japan office : kawasaki office : tel:+81-44-246-9100 fax:+81-44-246-9105 osaka office : tel:+81-6-4807-5460 fax:+81-6-4807-5461 singapore office : tel:+65-6346-5505 fax:+65-6348-8096 taipei office : tel:+886-2-2509-3300 fax:+886-2-2509-2200 m acronix a merica, i nc. tel:+1-408-262-8887 fax:+1-408-262-8810 http : //www.macronix.com macronix international co., ltd. reserves the right to change product and specifications without notice. |
Price & Availability of MX26F128J3XCC-15
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |